Introduction to SMD Packaging
SMD packaging technology is an abbreviation of Surface Mounted Devices packaging technology, meaning: Surface Mount devices, it is one of the Surface Mount Technology (SMT) components. In the initial stage of the production of electronic circuit boards, through-the-hole assembly is completely completed manually. When the first automated machines were introduced, they could place some simple pin components, but complex components still needed to be placed manually for wave soldering. Surface Mounted components (Surface Mounted components) are mainly rectangular chip components, cylindrical chip components, composite chip components, and shaped chip components.
In the initial stage of the production of electronic circuit boards, the hole assembly is completely completed manually. When the first automated machines were introduced, they could place some simple pin components, but complex components still needed to be placed manually for wave soldering.
What are the types of SMD packaging technology? _ Common Packaging Types
ball grid array (BGA)
Spherical contact display, one of the surface mount type packages. A spherical convex point is made on the back of the printed substrate according to the display mode to replace the pin, and the LSI chip is assembled on the front of the printed substrate, and then sealed with molded resin or potting method. Also known as raised point display carrier (PAC). The pin can be more than 200 and is a multi-pin LSI for a package.
The package body can also be made smaller than the QFP (four-sided pin flat package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; The QFP of pin 304 with a pin center distance of 0.5mm is 40mm square. And BGA doesn’t have to worry about pin distortion like QFP.
The package was developed by Motorola in the United States and was first adopted in devices such as portable phones and is likely to be popularized in personal computers in the United States in the future. Initially, the BGA had a pin (raised) center distance of 1.5mm and a pin number of 225. There are also some LSI manufacturers now developing 500-pin BGA.
The problem with BGA is the appearance inspection after reflow soldering. It is not clear whether the appearance inspection method is effective. Some believe that due to the large center distance of the welding, the connection can be regarded as stable and can only be handled by functional inspection.
The American Motorola company calls the package sealed with molded resin OMPAC, and the package sealed by potting method GPAC (see OMPAC and GPAC).
BQFP (quad flat package with bumper)
Four-sided pin flat package with cushioning. One of the QFP packages provides bumps (cushioning) at the four corners of the package body to prevent the pin from bending and deforming during transport. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The pin center distance is 0.635mm, and the number of pins ranges from 84 to around 196 (see QFP).
butt joint pin grid array (PGA)
Another name for surface mount PGA (see Surface Mount PGA).
A mark indicating a ceramic package. For example, CDIP stands for ceramic DIP. It is a sign that is often used in practice.
Ceramic dual-in-line package sealed with glass for ECL RAM, DSP (digital signal processor), and other circuits. Cerdip with glass window is used for UV-erasing EPROMs and microcomputer circuits with EPROMs inside. Pin center distance 2.54mm, pin number from 8 to 42. In Japan, this package is denoted as DIP-G (G means glass seal).
One of the surface mount type packages, that is, bottom-sealed ceramic QFP, is used to encapsulate logical LSI circuits such as DSPS. Cerquad with a window is used to encapsulate EPROM circuits. Heat dissipation is better than plastic QFP, and 1.5 ~ 2W power can be allowed under natural air cooling conditions. However, the packaging cost is 3 to 5 times higher than the plastic QFP. The center distance of the pin is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, and other specifications. Pin count from 32 to 368.
ceramic leaded chip carrier (CLCC)
Ceramic chip carrier with pins, one of the surface mount type packages, pins from the four sides of the package, in a T-shape. A window for encapsulating a UV-erasing EPROM and a microcomputer circuit with an EPROM, etc. This package is also called QFJ, QFJ-G (see QFJ).
COB (chip on board)
On-board chip packaging is one of the bare chip mounting technologies. The semiconductor chip is attached to the printed circuit board, the electrical connection between the chip and the substrate is realized by lead stitching, and the electrical connection between the chip and the substrate is realized by lead stitching, and the resin is covered to ensure reliability. Although COB is the simplest bare-chip mount technology, its package density is far less than TAB and backward technology.
DFP (dual flat package)
Two-sided pin flat package. Is another name for SOP (see SOP). The term used to be used, but it is no longer used.
DIC (dual in-line ceramic package) DIP (including glass seal) is another name.
DIL (dual in-line)
DIP (see DIP). European semiconductor manufacturers use this name.
DIP (dual in-line package)
Dual in-line package. In one of the plug-in-type packages, the pins lead from both sides of the package, and the packaging material is plastic and ceramic. DIP is the most popular plug-in package, the application range includes standard logic ics, memory LSI, microcomputer circuits, and so on. Pin center distance 2.54mm, pin number from 6 to 64. The package width is usually 15.2mm. Some packages with widths of 7.52mm and 10.16mm are called skinny DIP and slim DIP, respectively. However, in most cases, they do not make a distinction and are simply referred to as DIP. In addition, ceramic dips sealed with low-melting glass are also called CERdips.
DSO (dual small out-lint)
Two-sided pin small form factor package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.
DICP (dual tape carrier package)
Two-side pin on-load package. One of TCP (on-load encapsulation). Pins are made on insulating tape and lead from both sides of the package. Due to the use of TAB (Automatic on-load welding) technology, the package shape is very thin. Often used for liquid crystal display drives LSI, but most of the products. In addition, a 0.5mm thick memory LSI book-shaped package is under development. In Japan, DICP is named DTP according to the EIAJ (Japanese Electronic Machinery Industry) Association standard.
DIP (dual tape carrier package)
Ibid. The Japanese Electronic Machinery Industry will standardize the designation of DTCP (see DTCP).
FP (flat package)
Flat package. One of the surface mount type packages. QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.
Weld the chip backward. In one of the bare chip packaging technologies, the metal convex points are made in the electrode area of the LSI chip, and then the metal convex points are pressed and welded to the electrode area on the printed substrate. The footprint of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies.
However, if the coefficient of thermal expansion of the substrate is different from that of the LSI chip, there will be a reaction at the joint, thus affecting the reliability of the connection. Therefore, it is necessary to reinforce the LSI chip with resin and use a substrate material with basically the same coefficient of thermal expansion.
FQFP (fine pitch quad flat package)
Small pin center distance QFP. It is usually indicated that the foot center distance is less than 0.65mm QFP (see QFP). Some conductor manufacturers use this name.
CPAC (globe top pad array carrier) is another name for BGA by Motorola (see BGA).
CQFP (quad fiat package with guard ring)
Four-sided pin flat package with protective ring. In a plastic QFP, the pin is masked with a resin protective ring to prevent bending and deformation. Before assembling the LSI on the printed substrate, cut the pin from the protective ring and make it a seagull wing (L shape). The package has been mass-produced by Motorola in the United States. The pin center distance is 0.5mm, and the maximum number of pins is about 208.
H- (with heat sink)
Indicates a mark with a radiator. For example, HSOP stands for SOP with a radiator.
pin grid array (surface mount type)
Surface mount PGA. Usually, PGA is a plug-in package with a pin length of about 3.4mm. Surface-mount PGA has display pins on the underside of the package, ranging in length from 1.5mm to 2.0mm. The mounting adopts the method of touch welding with the printed substrate, so it is also called touch welding PGA. Because the pin center distance is only 1.27mm, half smaller than the plug-in PGA, the package body can be made not very large, and the number of pins is more than the plug-in type (250 ~ 528), which is a large-scale logical LSI package. The substrate of the package has a multi-layer ceramic substrate and a glass epoxy resin printing base. Packaging with multilayer ceramic substrate has been practical.
JLCC (J-leaded chip carrier)
J-pin chip carrier. Another name for windowed CLCC and windowed ceramic QFJ (see CLCC and QFJ). The name is used by some semiconductor manufacturers.
LCC (Leadless chip carrier)
Pin-less chip carrier. A surface-mount package in which the four sides of the ceramic substrate are only touched by electrodes without pins. Is a package for high-speed and high-frequency ics, also known as ceramic QFN or QFN-C (see QFN).
LGA (land grid array)
Contact display package. That is, a package with an array state tank electrode contact is made on the bottom side. Plug into the socket during assembly. Ceramic LGA with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance) are now available for high-speed logic LSI circuits.
LGA can accommodate more input/output pins in a smaller package than QFP. In addition, due to the small impedance of the lead, it is suitable for high-speed LSI. However, due to the complex production of sockets and high cost, they are basically not used now. Demand for them is expected to increase in the future.
26, LOC (lead on chip)
On-chip lead package. In one of the LSI packaging technologies, the front end of the lead frame is a structure above the chip, and the center of the chip is made with a convex solder joint, which is electrically connected with the lead suture. Compared with the original structure that arranged the lead frame near the side of the chip, the chip contained in the package of the same size is about 1mm wide.
LQFP (low profile quad flat package)
Thin QFP. Refers to the QFP with a body thickness of 1.4mm, which is the name used by the Japanese electronic machinery industry according to the new QFP form factor specification.
One of ceramic QFPS. Packaging substrate with aluminum nitride, base thermal conductivity is 7 to 8 times higher than alumina, with good heat dissipation. The encapsulated frame is made of alumina, and the chip is sealed by potting, which reduces costs. It is a package developed for logical LSI that allows W3 power under natural air cooling conditions. LSI logic packages with 208 pins (0.5mm center distance) and 160 pins (0.65mm center distance) have been developed and started mass production in October 1993.
MCM (multi-chip module)
Multi-chip components. A package in which multiple semiconductor bare chips are assembled on a single wiring substrate. According to the substrate material can be divided into MCM-L, MCM-C, and MCM-D three categories.
MCM-L is a component that uses the usual glass epoxy multilayer printed substrate. The wiring density is not very high, and the cost is low. MCM-C is a thick-film technology to form multi-layer wiring, with ceramic (alumina or glass ceramic) as a substrate component, similar to the thick film hybrid IC that uses a multi-layer ceramic substrate. There was no significant difference between the two. The wiring density is higher than MCM-L. MCM-D is a thin-film technology to form a multi-layer wiring, ceramic (alumina or aluminum nitride) or Si, Al as the substrate components. Cabling conspiracy is the highest of the three components, but the cost is also high.
MFP (mini flat package)
Small flat package. Plastic SOP or SSOP (see SOP and SSOP). The name is used by some semiconductor manufacturers.